| Presentation | 2009-12-14 An evaluation of delay error rate of an adder in terms of clock period Yuuta Ukon, Atsushi Takahashi, Kenji Taniguchi, |
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| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Currently, digital circuits are mainly realized as synchronous circuits that uses global clocks. In clock-synchronous circuit design, the reduction of clock period has been requested to improve the circuit performance. In complete-synchronous framework that is adopted as de facto standard in clock-synchronous circuit design, the maximum delay between Flip-Flops gives a lower bound of clock period. Therefore, the reduction of the maximum delay between Flip-Flops is pursued, but it approaches the limit. In this paper, we focus on the fact that the maximum delay varies depending on the input signal pattern, and introduce an error-detection-correction mechanism that enables a circuit to work with clock period which is less than the maximum delay. In order to confirm the effect of error-detection-correction mechanism, we evaluate the delay error rate of an adder and confirm that the effective clock period of the adder is reduced by introducing error-detection-correction mechanism. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Error-detection-correction mechanism / delay time / hold time / delay error rate / hold error rate / effective clock period |
| Paper # | ICD2009-91 |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 2009/12/7(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | An evaluation of delay error rate of an adder in terms of clock period |
| Sub Title (in English) | |
| Keyword(1) | Error-detection-correction mechanism |
| Keyword(2) | delay time |
| Keyword(3) | hold time |
| Keyword(4) | delay error rate |
| Keyword(5) | hold error rate |
| Keyword(6) | effective clock period |
| 1st Author's Name | Yuuta Ukon |
| 1st Author's Affiliation | Department of Engineering Electronics and Information Systems, Osaka University() |
| 2nd Author's Name | Atsushi Takahashi |
| 2nd Author's Affiliation | Division of Electrical, Electronic and Information Engineering, Osaka University |
| 3rd Author's Name | Kenji Taniguchi |
| 3rd Author's Affiliation | Division of Electrical, Electronic and Information Engineering, Osaka University |
| Date | 2009-12-14 |
| Paper # | ICD2009-91 |
| Volume (vol) | vol.109 |
| Number (no) | 336 |
| Page | pp.pp.- |
| #Pages | 5 |
| Date of Issue | |