Presentation	2009-12-14 Design Optimization of High-Speed, High-Gain OTA with g_m/I_D Lookup Table Method Takayuki KONISHI, Shoichi MASUI,
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Abstract(in English)	We propose a design optimization flow for a gain-boosted folded-cascode operational transconductance amplifier, which achieves high-speed and high-gain in a scaled CMOS technology, based on g_m/I_D lookup table design methodology. The design flow requires no tweak of circuit parameters by employing worst-case design scenarios and combination of analytical and simulation-based optimization process. The optimization flow is verified for the application to a residue amplifier in a 10-bit 100MS/s pipeline A/D converter in a 0.18μm CMOS technology.
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Keyword(in English)	operational transconductance amplifier / design optimization / analog design methodology / low power design
Paper #	ICD2009-84
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Conference Information
Committee	ICD
Conference Date	2009/12/7(1days)
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Paper Information
Registration To	Integrated Circuits and Devices (ICD)
Language	JPN
Title (in Japanese)	(See Japanese page)
Sub Title (in Japanese)	(See Japanese page)
Title (in English)	Design Optimization of High-Speed, High-Gain OTA with g_m/I_D Lookup Table Method
Sub Title (in English)
Keyword(1)	operational transconductance amplifier
Keyword(2)	design optimization
Keyword(3)	analog design methodology
Keyword(4)	low power design
1st Author's Name	Takayuki KONISHI
1st Author's Affiliation	Tohoku University()
2nd Author's Name	Shoichi MASUI
2nd Author's Affiliation	Tohoku University
Date	2009-12-14
Paper #	ICD2009-84
Volume (vol)	vol.109
Number (no)	336
Page	pp.pp.-
#Pages	6
Date of Issue