Presentation	2009-12-14 Modeling of power supply noise on CMOS digital circuits Daisuke FUJIMOTO, Tetsuro MATSUNO, Makoto NAGATA,
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Abstract(in English)	An arbitrary noise generator (ANG) is based on time-series charging of divided parasitic capacitance (TSDPC) and emulates power supply noise generation in a CMOS digital circuit. A prototype ANG incorporates an array of 32×32 6-bit TSDPC cells along with a 128-word vector memory and occupies 2×2 mm^2 in a 65 nm 1.2 V CMOS technology. Digital noise emulation of functional logic cores such as register arrays and processing elements is demonstrated with chip-level waveform monitoring at power supply, ground, as well as substrate nodes.
Keyword(in Japanese)	(See Japanese page)
Keyword(in English)	TSDPC model / Power supply noise
Paper #	ICD2009-82
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Conference Information
Committee	ICD
Conference Date	2009/12/7(1days)
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Paper Information
Registration To	Integrated Circuits and Devices (ICD)
Language	JPN
Title (in Japanese)	(See Japanese page)
Sub Title (in Japanese)	(See Japanese page)
Title (in English)	Modeling of power supply noise on CMOS digital circuits
Sub Title (in English)
Keyword(1)	TSDPC model
Keyword(2)	Power supply noise
1st Author's Name	Daisuke FUJIMOTO
1st Author's Affiliation	Kobe University()
2nd Author's Name	Tetsuro MATSUNO
2nd Author's Affiliation	Kobe University
3rd Author's Name	Makoto NAGATA
3rd Author's Affiliation	Kobe University
Date	2009-12-14
Paper #	ICD2009-82
Volume (vol)	vol.109
Number (no)	336
Page	pp.pp.-
#Pages	4
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