| Presentation | 2009-12-14 Design Technology of stacked NAND type 1-transistor FeRAM Koichi Sugano, Shigeyoshi Watanabe, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Design technology of stacked NAND type 1-transistor FeRAM has been described. With 39nm design rule feasibility study of 1T bit memory focused on cell array structure and core circuit has been investigated. 64 layer 8k×8k stacked SGT memory cellarray structure and the double ended row and column decoder with SGT have been newly introduced. From the estimation of wordline and bitline delay time this structure enables to reduce the delay time of core circuit to 5ns. Stacked NAND type 1-transistor FeRAM is a promising candidate for realizing fast access time of 50ns. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Design technology of stacked NAND type 1-transistor FeRAM has been described. With 39nm design rule feasibility study of 1T bit memory focused on cell array structure and core circuit has been investigated. 64 layer 8k×8k stacked SGT memory cellarray structure and the double ended row and column decoder with SGT have been newly introduced. From the estimation of wordline and bitline delay time this structure enables to reduce the delay time of core circuit to 5ns. Stacked NAND type 1-transistor FeRAM is a promising candidate for realizing fast access time of 50ns. / FeRAM / ferroelectric / stacked NAND structure |
| Paper # | ICD2009-80 |
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| Committee | ICD |
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| Conference Date | 2009/12/7(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Vice Chair | |
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| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Design Technology of stacked NAND type 1-transistor FeRAM |
| Sub Title (in English) | |
| Keyword(1) | Design technology of stacked NAND type 1-transistor FeRAM has been described. With 39nm design rule feasibility study of 1T bit memory focused on cell array structure and core circuit has been investigated. 64 layer 8k×8k stacked SGT memory cellarray structure and the double ended row and column decoder with SGT have been newly introduced. From the estimation of wordline and bitline delay time this structure enables to reduce the delay time of core circuit to 5ns. Stacked NAND type 1-transistor FeRAM is a promising candidate for realizing fast access time of 50ns. |
| Keyword(2) | FeRAM |
| Keyword(3) | ferroelectric |
| Keyword(4) | stacked NAND structure |
| 1st Author's Name | Koichi Sugano |
| 1st Author's Affiliation | Graduate School of Electrical and Information Engineering, Shonan Institute of Technology() |
| 2nd Author's Name | Shigeyoshi Watanabe |
| 2nd Author's Affiliation | Graduate School of Electrical and Information Engineering, Shonan Institute of Technology |
| Date | 2009-12-14 |
| Paper # | ICD2009-80 |
| Volume (vol) | vol.109 |
| Number (no) | 336 |
| Page | pp.pp.- |
| #Pages | 5 |
| Date of Issue | |