| Presentation | 2009-12-14 Design Technology of stacked type MRAM Shouto Tamai, Shigeyoshi Watanabe, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Design technology of stacked type MRAM using spin transistor has been described. Using 64 layer level cell structure featured by surrounded write bit line. Fast and low cost memory competitive to conventional NAND flash memory will be achieved. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Non-volatile memory / MRAM / stacked structure / Spin transistor |
| Paper # | ICD2009-79 |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 2009/12/7(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
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| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Design Technology of stacked type MRAM |
| Sub Title (in English) | |
| Keyword(1) | Non-volatile memory |
| Keyword(2) | MRAM |
| Keyword(3) | stacked structure |
| Keyword(4) | Spin transistor |
| 1st Author's Name | Shouto Tamai |
| 1st Author's Affiliation | Graduate School of Electrical and Information Engineering, Shonan Institute of Technology() |
| 2nd Author's Name | Shigeyoshi Watanabe |
| 2nd Author's Affiliation | Graduate School of Electrical and Information Engineering, Shonan Institute of Technology |
| Date | 2009-12-14 |
| Paper # | ICD2009-79 |
| Volume (vol) | vol.109 |
| Number (no) | 336 |
| Page | pp.pp.- |
| #Pages | 5 |
| Date of Issue | |