| Presentation | 2009-12-14 Reducing pattern area technology of 3D transistor for system LSI Yu Hiroshima, Shigeyoshi Watanabe, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | We designed 1 bit Full Adder with FinFET, Double-Gate transistor. FinFET, Double-Gate transistor, Stacked type transistor designed by composite gate can be reduced 20.05%, 18.39%, 16.40% compared with that using planar transistor designed by only NAND, Inverter. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | FinFET / Independent-gate controlled Double-Gate transistor / Stacked type 3D transistor / Full adder / system LSI |
| Paper # | ICD2009-78 |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 2009/12/7(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
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| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Reducing pattern area technology of 3D transistor for system LSI |
| Sub Title (in English) | |
| Keyword(1) | FinFET |
| Keyword(2) | Independent-gate controlled Double-Gate transistor |
| Keyword(3) | Stacked type 3D transistor |
| Keyword(4) | Full adder |
| Keyword(5) | system LSI |
| 1st Author's Name | Yu Hiroshima |
| 1st Author's Affiliation | Graduate School of Electrical and Information Engineering, Shonan Institute of Technology() |
| 2nd Author's Name | Shigeyoshi Watanabe |
| 2nd Author's Affiliation | Graduate School of Electrical and Information Engineering, Shonan Institute of Technology |
| Date | 2009-12-14 |
| Paper # | ICD2009-78 |
| Volume (vol) | vol.109 |
| Number (no) | 336 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |