Presentation 2009-12-14
Experimental Evaluation Technique for Power Supply Noise and Logical Operation Failure
Mitsuya FUKAZAWA, Makoto NAGATA,
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Abstract(in English) Logical operations in CMOS digital integration are highly prone to fail as the amount of power supply (PS) drop approaches to failure threshold. PS voltage variation is characterized by built-in noise monitors in a 32-bit microprocessor of 90-nm CMOS technology, and related with operation failures by instruction-level programming for logical failure analysis. Combination of voltage drop size and activated logic path determines failure sensitivity and class of failures. Experimental observation as well as simplified simulation is applied for the detailed understanding of the impact of PS noise on logical operations of digital integrated circuits.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) dynamic power supply noise / built-in probing circuit / logical operation failure / dynamic frequency scaling
Paper # ICD2009-77
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Committee ICD
Conference Date 2009/12/7(1days)
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Registration To Integrated Circuits and Devices (ICD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Experimental Evaluation Technique for Power Supply Noise and Logical Operation Failure
Sub Title (in English)
Keyword(1) dynamic power supply noise
Keyword(2) built-in probing circuit
Keyword(3) logical operation failure
Keyword(4) dynamic frequency scaling
1st Author's Name Mitsuya FUKAZAWA
1st Author's Affiliation Renesas Technology Corporation()
2nd Author's Name Makoto NAGATA
2nd Author's Affiliation Dept. of Computer Science and Systems Engineering, Kobe University
Date 2009-12-14
Paper # ICD2009-77
Volume (vol) vol.109
Number (no) 336
Page pp.pp.-
#Pages 6
Date of Issue