Presentation 2010-03-05
A PLL Synthesizer Composed of Parallel Dual Modulus Prescaler with a step size of 0.5
Hideyuki NAKAMIZO, Kenichi TAJIMA, Ryoji HAYAHSI, TOSHIYA Uozumi,
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Abstract(in English) By reducing the step size of the programmable frequency divider in Fractional-N PLL from 1 to 0.5, the phase noise contributed by the fractional division is reduced by 6dB. This paper shows a PLL synthesizer composed of a pulse swallow programmable divider with the division step size is 0.5. To realize the division step size of 0.5, we propose a parallel dual modulus prescaler architecture with a division factor P or P+0.5. The PLL synthesizer with the proposed parallel dual modulus prescaler is implemented in a 0.13-nm CMOS process and confirmed the characteristics at 5GHz.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Phase Lock loop / Fractional-N / Divider / Dual Modulus Prescaler / Phase Noise
Paper # MW2009-209
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Committee MW
Conference Date 2010/2/25(1days)
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Registration To Microwaves (MW)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A PLL Synthesizer Composed of Parallel Dual Modulus Prescaler with a step size of 0.5
Sub Title (in English)
Keyword(1) Phase Lock loop
Keyword(2) Fractional-N
Keyword(3) Divider
Keyword(4) Dual Modulus Prescaler
Keyword(5) Phase Noise
1st Author's Name Hideyuki NAKAMIZO
1st Author's Affiliation Mitsubishi Electric Corporation()
2nd Author's Name Kenichi TAJIMA
2nd Author's Affiliation Mitsubishi Electric Corporation
3rd Author's Name Ryoji HAYAHSI
3rd Author's Affiliation Mitsubishi Electric Corporation
4th Author's Name TOSHIYA Uozumi
4th Author's Affiliation Renesas Technology Corp
Date 2010-03-05
Paper # MW2009-209
Volume (vol) vol.109
Number (no) 431
Page pp.pp.-
#Pages 4
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