Presentation 2010-04-23
A Fast-acquisition PLL Using a Fully Digital Natural-frequency-switching Technique
Mitsuo NAKAMURA, Akihiro YAMAGISHI, Mitsuru HARADA, Makoto NAKAMURA,
PDF Download Page PDF download Page Link
Abstract(in Japanese) (See Japanese page)
Abstract(in English) A new PLL with a simple architecture that overcomes the trade-off between the acquisition time and phase noise was in a 0.2-μm CMOS process. One-fifth the acquisition time of the integer-N is achieved by switching only the division ratio with the optimized damping factor to control the natural frequency.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) PLL / Fast-acquisition / Natural Frequency
Paper # SCE2010-13,MW2010-13
Date of Issue

Conference Information
Committee SCE
Conference Date 2010/4/16(1days)
Place (in Japanese) (See Japanese page)
Place (in English)
Topics (in Japanese) (See Japanese page)
Topics (in English)
Chair
Vice Chair
Secretary
Assistant

Paper Information
Registration To Superconductive Electronics (SCE)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A Fast-acquisition PLL Using a Fully Digital Natural-frequency-switching Technique
Sub Title (in English)
Keyword(1) PLL
Keyword(2) Fast-acquisition
Keyword(3) Natural Frequency
1st Author's Name Mitsuo NAKAMURA
1st Author's Affiliation NTT Microsystem Integration Laborartories()
2nd Author's Name Akihiro YAMAGISHI
2nd Author's Affiliation NTT Microsystem Integration Laborartories
3rd Author's Name Mitsuru HARADA
3rd Author's Affiliation NTT Microsystem Integration Laborartories
4th Author's Name Makoto NAKAMURA
4th Author's Affiliation NTT Photonics Laborartories
Date 2010-04-23
Paper # SCE2010-13,MW2010-13
Volume (vol) vol.110
Number (no) 13
Page pp.pp.-
#Pages 5
Date of Issue