| Presentation | 2010-05-14 An Efficient Implementation of Exhaustive Verification of the Collatz Conjecture using DSP48E blocks of Xilinx Virtex-5 FPGAs Yasuaki ITO, Koji NAKANO, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Consider the following operation on an arbitrary positive number: if the number is even, divide it by two, and if the number is odd, triple it and add one. The Collatz conjecture asserts that, starting from any positive number m, repeated iteration of the operations eventually produces the value 1. The main contribution of this paper is to present an efficient implementation of a coprocessor that performs the exhaustive search to verify the Collatz conjecture using a DSP48E Xilinx Virtex-5 blocks, each of which contains one multiplier and one adder. The experimental results show that, our coprocessor can verify 3.88×10^8 64-bit numbers per second. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Hardware Algorithm / Collatz conjecture / FPGA Implementation / DSP blocks / block RAMs |
| Paper # | RECONF2010-15 |
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| Conference Information | |
| Committee | RECONF |
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| Conference Date | 2010/5/6(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Reconfigurable Systems (RECONF) |
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| Language | ENG |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | An Efficient Implementation of Exhaustive Verification of the Collatz Conjecture using DSP48E blocks of Xilinx Virtex-5 FPGAs |
| Sub Title (in English) | |
| Keyword(1) | Hardware Algorithm |
| Keyword(2) | Collatz conjecture |
| Keyword(3) | FPGA Implementation |
| Keyword(4) | DSP blocks |
| Keyword(5) | block RAMs |
| 1st Author's Name | Yasuaki ITO |
| 1st Author's Affiliation | Department of Information Engineering, Hiroshima University() |
| 2nd Author's Name | Koji NAKANO |
| 2nd Author's Affiliation | Department of Information Engineering, Hiroshima University |
| Date | 2010-05-14 |
| Paper # | RECONF2010-15 |
| Volume (vol) | vol.110 |
| Number (no) | 32 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |