| Presentation | 2010-05-13 First Prototype Chip of a Non-Volatile Reconfigurable Logic using FeRAM Cells Masahiro KOGA, Masahiro IIDA, Motoki AMAGASAKI, Yoshinobu ICHIDA, Mitsuro SAJI, Jun IIDA, Toshinori SUEYOSHI, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | An advantage of a RLD such as an FPGA is that it can be customized after being manufactured. However, there is a problem related to standby power when using it in SoC used in embedded systems. Power gating, which is one of the power reduction techniques, is difficult to use in SRAM-based RLDs because of the high overhead and SRAM being volatile. In this paper, we describe a chip that we developed - a reconfigurable logic chip based on FeRAM technology. The chip uses a variable grain logic cell as a logic block. A NV-FF(Non-Volatile FlipFlop), which contains FeRAM, a FF, and power-gating control circuits, is used as configuration memory. The NV-FF can transmit data between FeRAM and FF automatically when power to the chip is turned off/on. The hibernate/restore time is less than 1 ms. The chip has 18 × 18 logic blocks and an area of 54.76 mm^2. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Prototype / Reconfigurable logic / Power gating / Non-volatile memory |
| Paper # | RECONF2010-5 |
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| Committee | RECONF |
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| Conference Date | 2010/5/6(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Registration To | Reconfigurable Systems (RECONF) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | First Prototype Chip of a Non-Volatile Reconfigurable Logic using FeRAM Cells |
| Sub Title (in English) | |
| Keyword(1) | Prototype |
| Keyword(2) | Reconfigurable logic |
| Keyword(3) | Power gating |
| Keyword(4) | Non-volatile memory |
| 1st Author's Name | Masahiro KOGA |
| 1st Author's Affiliation | Graduate School of Science and Technology, Kumamoto University() |
| 2nd Author's Name | Masahiro IIDA |
| 2nd Author's Affiliation | Graduate School of Science and Technology, Kumamoto University |
| 3rd Author's Name | Motoki AMAGASAKI |
| 3rd Author's Affiliation | Graduate School of Science and Technology, Kumamoto University |
| 4th Author's Name | Yoshinobu ICHIDA |
| 4th Author's Affiliation | KTC LSI Development Headquarters, ROHM Co., Ltd. |
| 5th Author's Name | Mitsuro SAJI |
| 5th Author's Affiliation | KTC LSI Development Headquarters, ROHM Co., Ltd. |
| 6th Author's Name | Jun IIDA |
| 6th Author's Affiliation | LSI Development Headquarters, ROHM Co., Ltd. |
| 7th Author's Name | Toshinori SUEYOSHI |
| 7th Author's Affiliation | Graduate School of Science and Technology, Kumamoto University |
| Date | 2010-05-13 |
| Paper # | RECONF2010-5 |
| Volume (vol) | vol.110 |
| Number (no) | 32 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |