Presentation 2010-05-13
An FPGA implementation of Full-search variable block size motion Estimation
Shuichi ASANO, ZhiShun ZHENG, Tsutomu MARUYAMA,
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Abstract(in English) In this paper, we propose an approach for full-search variable block size motion estimation using an FPGA. We can realize the real-time processing of DVD frames with a small size FPGA when the search range is [-32,+32]×[-32,+32]. Our approach is scalable in the practical range, and can realize the real-time processing of HD frames when the search range is [-64,+64]×[-64,+64], though it requires 16 times hardware resources. In this case, it is possible to enlarge the size of the macroblock to 64 × 64 pixels.
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Keyword(in English) FPGA / Full-search / Motion Estimation
Paper # RECONF2010-2
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Conference Information
Committee RECONF
Conference Date 2010/5/6(1days)
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Registration To Reconfigurable Systems (RECONF)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) An FPGA implementation of Full-search variable block size motion Estimation
Sub Title (in English)
Keyword(1) FPGA
Keyword(2) Full-search
Keyword(3) Motion Estimation
1st Author's Name Shuichi ASANO
1st Author's Affiliation Systems and Information Engineering, University of Tsukuba()
2nd Author's Name ZhiShun ZHENG
2nd Author's Affiliation Systems and Information Engineering, University of Tsukuba
3rd Author's Name Tsutomu MARUYAMA
3rd Author's Affiliation Systems and Information Engineering, University of Tsukuba
Date 2010-05-13
Paper # RECONF2010-2
Volume (vol) vol.110
Number (no) 32
Page pp.pp.-
#Pages 6
Date of Issue