| Presentation | 2009-12-04 Implementation of core functions of a H264 encoder on STP-engine Yoshihiro TAKAMATSU, Hideharu AMANO, Takao TOI, |
|---|---|
| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | A dynamic image compression standard H.264 achieves much more compression ratio than traditional standards, but requires a large computation power which cannot be supported by software on embedded processors. Dynamically reconfigurable processors which provides both flexibility and power efficiency is a candidate of off-loading engine for H.264 coder. However, the practical implementation has rarely reported especially on the encoder which is consisting of complicated task chain. NEC electronics' STP engine provides the 2nd generation dynamically reconfigurable processor core and a sophisticated DMA mechanism which enables to implement complicated tasks. As the first step of implementation of H.264 encoder on STP engine, two time consuming tasks are implemented on STP engine. By using parallel reading from distributed memory and balanced tree, 11 times performance is achieved compared with a popular embedded CPU MIPS R3000 which works 266MHz. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Dynamically Reconfigurable Processor / H.264 / Off-loading |
| Paper # | RECONF2009-53 |
| Date of Issue |
| Conference Information | |
| Committee | RECONF |
|---|---|
| Conference Date | 2009/11/26(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Reconfigurable Systems (RECONF) |
|---|---|
| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Implementation of core functions of a H264 encoder on STP-engine |
| Sub Title (in English) | |
| Keyword(1) | Dynamically Reconfigurable Processor |
| Keyword(2) | H.264 |
| Keyword(3) | Off-loading |
| 1st Author's Name | Yoshihiro TAKAMATSU |
| 1st Author's Affiliation | Faculty of Science and Technology, Keio University() |
| 2nd Author's Name | Hideharu AMANO |
| 2nd Author's Affiliation | Faculty of Science and Technology, Keio University |
| 3rd Author's Name | Takao TOI |
| 3rd Author's Affiliation | Faculty of Science and Technology, Keio University |
| Date | 2009-12-04 |
| Paper # | RECONF2009-53 |
| Volume (vol) | vol.109 |
| Number (no) | 320 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |