| Presentation | 2009-12-04 A Project on Dynamically Reconfigurable Processors: MuCCRA : Design environment, Low Power design and 3D wireless interconnect Hideharu AMANO, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Dynamically reconfigurable processor project MuCCRA(Multi-Core Configurable Reconfigurable Architecture)aims to establish an environment which can generate a multi-core dynamically reconfigurable systems optimized for its target application. The following researches are exerted for such an environment: (1) Analysis of the architectural trade-off between performance, area and power influenced by PE instruction, array size and interconnection network. (2) Proposing new ideas to optimize context control mechanism, configuration data transfer and context memory which improve any type of cores. (3) Analysis and improving the energy efficiency which is the most promising feature compared with other accelerators. (4) Introducing 3D wireless interconnected structure for scalable extension of the performance after chip fabrication. This report introduces recent research results of the project. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Dynamically Reconfigurable Processor / Low Power Design / 3D wireless interconnect |
| Paper # | RECONF2009-51 |
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| Conference Information | |
| Committee | RECONF |
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| Conference Date | 2009/11/26(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Registration To | Reconfigurable Systems (RECONF) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Project on Dynamically Reconfigurable Processors: MuCCRA : Design environment, Low Power design and 3D wireless interconnect |
| Sub Title (in English) | |
| Keyword(1) | Dynamically Reconfigurable Processor |
| Keyword(2) | Low Power Design |
| Keyword(3) | 3D wireless interconnect |
| 1st Author's Name | Hideharu AMANO |
| 1st Author's Affiliation | Faculty of Science and Technology, Keio University() |
| Date | 2009-12-04 |
| Paper # | RECONF2009-51 |
| Volume (vol) | vol.109 |
| Number (no) | 320 |
| Page | pp.pp.- |
| #Pages | 6 |
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