| Presentation | 2009-12-04 A Study of two input LUT array type programmable logic architecture for cryptographic processing Ai NAKANISHI, Kouta ISHIBASHI, Yuuichirou KUROKAWA, Takeshi FUJINO, |
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| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Various kinds of block ciphers must be supported in order to communicate safely in computer networks by using the consumer electric appliances or the mobile devices. The high-speed encryption cannot be realized by the software implementation on low-performance CPU. The dedicated encryption hardware in the ASIC represents high performance, however, the handling of newly-developed cipher algorithm is difficult. In this study, we examined the novel programmable logic architecture which supports various kinds of cipher algorism by changing configuration data. This programmable logic architecture composed of two components; one is the ePLXcrypt which calculate bit-wise operation, the other is the MEMcrypt which calculate S-Box operation. The ePLXcrypt is modified for cipher processing from the conventional ePLX architecture in order to reduce macro area. The MEMcrypt, which calculate SBox procedure in DES and AES cipher, is designed by verilog HDL, and verified by Modelsim. The area estimation of MEMcrypt is also carried out by SRAM cell layout using 0.18 um CMOS process. We investigated the MEMcrypt area by comparing the chip area estimation derived from logic synthesis. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | programmable device / LUT matrix / encryption circuit |
| Paper # | RECONF2009-49 |
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| Conference Information | |
| Committee | RECONF |
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| Conference Date | 2009/11/26(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Reconfigurable Systems (RECONF) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Study of two input LUT array type programmable logic architecture for cryptographic processing |
| Sub Title (in English) | |
| Keyword(1) | programmable device |
| Keyword(2) | LUT matrix |
| Keyword(3) | encryption circuit |
| 1st Author's Name | Ai NAKANISHI |
| 1st Author's Affiliation | Graduate School of Science and Engineering, Ritsumeikan University() |
| 2nd Author's Name | Kouta ISHIBASHI |
| 2nd Author's Affiliation | Graduate School of Science and Engineering, Ritsumeikan University |
| 3rd Author's Name | Yuuichirou KUROKAWA |
| 3rd Author's Affiliation | Graduate School of Science and Engineering, Ritsumeikan University |
| 4th Author's Name | Takeshi FUJINO |
| 4th Author's Affiliation | Faculty of Science and Engineering, Ritsumeikan University |
| Date | 2009-12-04 |
| Paper # | RECONF2009-49 |
| Volume (vol) | vol.109 |
| Number (no) | 320 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |