| Presentation | 2009-12-03 Development of Standard Evaluation Environment for Side-channel Attacks and Countermeasures Toshihiro KATASHITA, Yohei HORI, Akashi SATOH, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Cryptography used widely in electronic products is evaluated in terms of computationally-secure, however there is vulnerability of hardware modules to physical attacks by defective implementation of the cryptographic algorithm. Side-channel attacks, which are categorized as noninvasive physical attacks, are considered serious threats to cryptographic modules, and countermeasures and evaluation methods are researched. We have developed and distributed standard evaluation FPGA boards for Side-channel attack evaluation. We have also implemented several AES circuits with DPA countermeasures on the FPGA boards, although the countermeasures require at least 2 times as many logic gates as general AES circuit. The logic capacity of the board is not sufficient for the implementation of more advanced research. In this paper, we develop a new evaluation board in order to improve the functionality of the device. We evaluate the logic capacity and the analog characteristics for side-channel attack experiments and logic capability for countermeasure circuit by comparing between previous and new boards. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | FPGA / Cryptography / Side-channel attack / Standard evaluation environment |
| Paper # | RECONF2009-46 |
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| Conference Information | |
| Committee | RECONF |
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| Conference Date | 2009/11/26(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Registration To | Reconfigurable Systems (RECONF) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Development of Standard Evaluation Environment for Side-channel Attacks and Countermeasures |
| Sub Title (in English) | |
| Keyword(1) | FPGA |
| Keyword(2) | Cryptography |
| Keyword(3) | Side-channel attack |
| Keyword(4) | Standard evaluation environment |
| 1st Author's Name | Toshihiro KATASHITA |
| 1st Author's Affiliation | Research Center for Information Security, National Institute of Advanced Industrial Science and Technology() |
| 2nd Author's Name | Yohei HORI |
| 2nd Author's Affiliation | Research and Development Initiative, Chuo University |
| 3rd Author's Name | Akashi SATOH |
| 3rd Author's Affiliation | Research Center for Information Security, National Institute of Advanced Industrial Science and Technology |
| Date | 2009-12-03 |
| Paper # | RECONF2009-46 |
| Volume (vol) | vol.109 |
| Number (no) | 320 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |