Presentation 2010-06-11
Hardware Implementation of Real-time Deinterlacing based on Inpainting
Tatsuo MAENO, Hiroshi TSUTSUI, Takao ONOYE,
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Abstract(in English) In this paper, we propose a novel hardware architecture for inpainting-based deinterlacing method, which can convert 1080i60 video data to 1080p60 in real-time. Interlaced video sequences are widely used for digital terrestrial television and camcorders. However, they cannot be displayed directly on LCDs, which display video sequences by progressive scanning. Therefore, it is necessary to convert video sequences from interlaced format to progressive format. Recently proposed inpainting-based deinterlacing uses cost optimization to interpolate missing lines, which can be solved likely shortest path problem. Since this method does not require motion estimation, it is expected that implementations of this method require smaller amount of memory bits compared to methods based on motion compensation. In this paper, the number of processing elements in our architecture, which affects both converted video quality and hardware cost, is evaluated. When the number of processing elements which gives best video quality with reasonable hardware cost is used, the gate count of the proposed architecture is 942,998, and required memory size is 399 Kbit.
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Keyword(in English) Deinterlace / IP conversion / Real-time processing / Inpainting
Paper # SIS2010-16
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Committee SIS
Conference Date 2010/6/3(1days)
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Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Hardware Implementation of Real-time Deinterlacing based on Inpainting
Sub Title (in English)
Keyword(1) Deinterlace
Keyword(2) IP conversion
Keyword(3) Real-time processing
Keyword(4) Inpainting
1st Author's Name Tatsuo MAENO
1st Author's Affiliation Dept. of Information Systems Engineering, Graduate School of Information Science and Technology, Osaka University()
2nd Author's Name Hiroshi TSUTSUI
2nd Author's Affiliation Dept. of Communications and Computer Engineering, Graduate School of Informatics, Kyoto University
3rd Author's Name Takao ONOYE
3rd Author's Affiliation Dept. of Information Systems Engineering, Graduate School of Information Science and Technology, Osaka University
Date 2010-06-11
Paper # SIS2010-16
Volume (vol) vol.110
Number (no) 74
Page pp.pp.-
#Pages 6
Date of Issue