Presentation 2010-06-10
Reducation of Memory Area and Power Consumption Using FIFO for HMM-based Speech Recognition Circuits
Katsuya TAKAHASHI, Shingo YOSHIZAWA, Noboru HAYASAKA, Yoshikazu MIYANAGA,
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Abstract(in English) This paper proposes reduction of memory area and power using FIFO for HMM-based speech recognition system. In conventional method, buffering HMM-parameter in the register has made computations of output probability more faster. However, it has a problem that increasing the number of feature vector causes enlarging memory area. In proposal method, exchanging register for FIFO(First In First Out) realizes reduction of memory area. And the number of access is decreased by changing order of computing.
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Keyword(in English) Speech Recognition / Parallel Signal Processing / VLSI
Paper # SIS2010-7
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Committee SIS
Conference Date 2010/6/3(1days)
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Language JPN
Title (in Japanese) (See Japanese page)
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Title (in English) Reducation of Memory Area and Power Consumption Using FIFO for HMM-based Speech Recognition Circuits
Sub Title (in English)
Keyword(1) Speech Recognition
Keyword(2) Parallel Signal Processing
Keyword(3) VLSI
1st Author's Name Katsuya TAKAHASHI
1st Author's Affiliation Graduate School of Information Science and Technology Hokkaido University()
2nd Author's Name Shingo YOSHIZAWA
2nd Author's Affiliation Graduate School of Information Science and Technology Hokkaido University
3rd Author's Name Noboru HAYASAKA
3rd Author's Affiliation RayTron ,INC
4th Author's Name Yoshikazu MIYANAGA
4th Author's Affiliation Graduate School of Information Science and Technology Hokkaido University
Date 2010-06-10
Paper # SIS2010-7
Volume (vol) vol.110
Number (no) 74
Page pp.pp.-
#Pages 6
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