| Presentation | 2010-06-25 High Sensitive Clock Extraction for a 160Gbit/s OTDM Signal Shigehiro TAKASAKA, Yu MIMURA, Takeshi YAGI, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | We have demonstrated a high sensitive clock recovery using an optoelectronic phase-locked loop (PLL). High trans-impedance of 62 k Ω can be applied to a photo-receiver as a result of a low intermediate frequency of 10.7 MHz reduced by employing a SSB modulation. The recovered 10-GHz RF clock has timing jitter less than 101fs(RMS) over the input signal power range from -10 to 1 dBm. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Clock extraction / Clock recovery / 160Gbit/s / OTDM / Optoelectronics / Phase-Locked Loop |
| Paper # | OCS2010-18 |
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| Conference Information | |
| Committee | OCS |
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| Conference Date | 2010/6/17(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Optical Communication Systems (OCS) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | High Sensitive Clock Extraction for a 160Gbit/s OTDM Signal |
| Sub Title (in English) | |
| Keyword(1) | Clock extraction |
| Keyword(2) | Clock recovery |
| Keyword(3) | 160Gbit/s |
| Keyword(4) | OTDM |
| Keyword(5) | Optoelectronics |
| Keyword(6) | Phase-Locked Loop |
| 1st Author's Name | Shigehiro TAKASAKA |
| 1st Author's Affiliation | FITEL photonics laboratory, Furukawa Electric Co., Ltd.() |
| 2nd Author's Name | Yu MIMURA |
| 2nd Author's Affiliation | FITEL photonics laboratory, Furukawa Electric Co., Ltd. |
| 3rd Author's Name | Takeshi YAGI |
| 3rd Author's Affiliation | FITEL photonics laboratory, Furukawa Electric Co., Ltd. |
| Date | 2010-06-25 |
| Paper # | OCS2010-18 |
| Volume (vol) | vol.110 |
| Number (no) | 94 |
| Page | pp.pp.- |
| #Pages | 5 |
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