Presentation 2010-06-21
Layout-aware Variation Modeling and Its Application to Op-Amp Design
Kouta SHINOHARA, Mihoko HIDAKA, Qing DONG, Jing LI, Shigetoshi NAKATAKE,
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Abstract(in English) As geometrical scaling of the transistor dimensions, such as feature size and supply voltage, has dominated the semiconductor industry for greater chip density, the variation analysis of transistor characteristic also becomes more critical important for analog integrated circuit design. In this paper, we present a model for the layout structure dependent variation according to the variation data got from a TEG (test element group) chip, then a correlation analysis is made between the result of Monte Carlo analysis based on this model and the experimental verification result for the offset voltage variation in a 90nm Op-Amp.
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Keyword(in English) analog layout design / layout-aware variation / Monte Carlo analysis / Op-Amp design
Paper # CAS2010-7,VLD2010-17,SIP2010-28,CST2010-7
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Committee VLD
Conference Date 2010/6/14(1days)
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Registration To VLSI Design Technologies (VLD)
Language ENG
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Layout-aware Variation Modeling and Its Application to Op-Amp Design
Sub Title (in English)
Keyword(1) analog layout design
Keyword(2) layout-aware variation
Keyword(3) Monte Carlo analysis
Keyword(4) Op-Amp design
1st Author's Name Kouta SHINOHARA
1st Author's Affiliation ()
2nd Author's Name Mihoko HIDAKA
2nd Author's Affiliation
3rd Author's Name Qing DONG
3rd Author's Affiliation
4th Author's Name Jing LI
4th Author's Affiliation
5th Author's Name Shigetoshi NAKATAKE
5th Author's Affiliation
Date 2010-06-21
Paper # CAS2010-7,VLD2010-17,SIP2010-28,CST2010-7
Volume (vol) vol.110
Number (no) 87
Page pp.pp.-
#Pages 5
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