Presentation | 2010-06-21 Clocking Pattern Minimization for Adjustable Safe Clocking-Based Register Assignment Keisuke INOUE, Mineo KANEKO, |
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Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | This work focuses on the timing variation-aware datapath design based on Contra-Data-Direction (CDD) clocking. Although a register assignment based on CDD clocking has been proposed, resultant datapaths suffer from the increase in registers. To overcome the problem, this paper proposes a novel timing variation-aware design using Adjustable CDD (ACDD) clocking, named ACDD-based design. An ILP-based approach is presented to minimize the cost of ACDD clocking, which is a fundamental problem in ACDD-based design. Experiments show the effectiveness of the approach. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | Register assignment / adjustable safe clocking / integer linear programming |
Paper # | CAS2010-1,VLD2010-11,SIP2010-22,CST2010-1 |
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Committee | VLD |
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Conference Date | 2010/6/14(1days) |
Place (in Japanese) | (See Japanese page) |
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Registration To | VLSI Design Technologies (VLD) |
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Language | ENG |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | Clocking Pattern Minimization for Adjustable Safe Clocking-Based Register Assignment |
Sub Title (in English) | |
Keyword(1) | Register assignment |
Keyword(2) | adjustable safe clocking |
Keyword(3) | integer linear programming |
1st Author's Name | Keisuke INOUE |
1st Author's Affiliation | School of Information Science, Japan Advanced Institute of Science and Technology (JAIST):Japan Society for the Promotion of Science (JSPS)() |
2nd Author's Name | Mineo KANEKO |
2nd Author's Affiliation | School of Information Science, Japan Advanced Institute of Science and Technology (JAIST) |
Date | 2010-06-21 |
Paper # | CAS2010-1,VLD2010-11,SIP2010-22,CST2010-1 |
Volume (vol) | vol.110 |
Number (no) | 87 |
Page | pp.pp.- |
#Pages | 6 |
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