| Presentation | 2010-06-22 Study of pattern area reduction for System LSI with SGT and stacked SGT Takahiro KODAMA, Shigeyoshi WATANABE, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | The pattern area reduction of inverter, NAND, and full adder with SGT and stacked SGT has been 'newly' estimated. Wring SGT and stacked SGT the pattern area can be drastically reduced compared with that of conventional planar transistor, SGT and stacked SGT are promising candidate for reeling high density system LSI. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | SGT / stacked SGT / system LSI / design rule / pattern area |
| Paper # | SDM2010-45 |
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| Conference Information | |
| Committee | SDM |
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| Conference Date | 2010/6/15(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
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| Paper Information | |
| Registration To | Silicon Device and Materials (SDM) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Study of pattern area reduction for System LSI with SGT and stacked SGT |
| Sub Title (in English) | |
| Keyword(1) | SGT |
| Keyword(2) | stacked SGT |
| Keyword(3) | system LSI |
| Keyword(4) | design rule |
| Keyword(5) | pattern area |
| 1st Author's Name | Takahiro KODAMA |
| 1st Author's Affiliation | () |
| 2nd Author's Name | Shigeyoshi WATANABE |
| 2nd Author's Affiliation | |
| Date | 2010-06-22 |
| Paper # | SDM2010-45 |
| Volume (vol) | vol.110 |
| Number (no) | 90 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |