| Presentation | 2010-06-25 An I/O Sequence Slicing Method for Post-silicon Debugging Yeonbok LEE, Takeshi MATSUMOTO, Masahiro FUJITA, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | For today's large-scaled and complicated LSI designs, post-silicon debugging process is becoming the crucial to shorten the time-to-market. In post-silicon debugging, the most critical problems are low observability and long execution trace. In this paper, we propose a method to generate a circuit that analyzes the dependencies between the signal values in an execution, and output the timings of the input signal values that influence on a particular output value. The number of the input values obtained by executing the circuit is smaller than the number of input values included in the original sequence, hence we can save the effort in debugging. We prepared several design examples, and generated the circuits to achieve our proposed method. The area overhead of the generated circuits were 4% in average. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Post-silicon debugging / I/O sequence slicing |
| Paper # | DC2010-13 |
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| Conference Information | |
| Committee | DC |
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| Conference Date | 2010/6/18(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Dependable Computing (DC) |
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| Language | ENG |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | An I/O Sequence Slicing Method for Post-silicon Debugging |
| Sub Title (in English) | |
| Keyword(1) | Post-silicon debugging |
| Keyword(2) | I/O sequence slicing |
| 1st Author's Name | Yeonbok LEE |
| 1st Author's Affiliation | Department of Electronics Engineering, School of Engineering, University of Tokyo() |
| 2nd Author's Name | Takeshi MATSUMOTO |
| 2nd Author's Affiliation | VLSI Design and Education Center, University of Tokyo |
| 3rd Author's Name | Masahiro FUJITA |
| 3rd Author's Affiliation | VLSI Design and Education Center, University of Tokyo:CREST, Japan Science and Technology Agency (JST) |
| Date | 2010-06-25 |
| Paper # | DC2010-13 |
| Volume (vol) | vol.110 |
| Number (no) | 106 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |