| Presentation | 2010-06-25 A test pattern matching method on BAST architecture using don't care identification for the detection of random pattern resistant faults Yun Chen, Toshinori HOSOKAWA, Masayoshi YOSHIMURA, |
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| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | BAST is one of techniques which are combined ATPG and BIST to reduce the amount of test data while maintaining the high test quality. On BAST architecture, a bit-flipping technique is used to convert pseudo-random patterns to deterministic patterns. In this paper, we use a don't care identification technique for random-pattern resistant faults which identifies unnecessary signal value to detect the fault set as don't care bits. Random-pattern resistant faults are defined that those detection time by a given test pattern set is equal or less than N. We propose a method of mapping between a pseudo-random pattern set and a deterministic pattern set for random-pattern resistant faults to which don't care identification technique is applied. We also evaluate the relationship among the number of random-pattern resistant faults, the number of don't care bits, the number of undetected faults, the number of bit-flips, and test application time for ITC'99 benchmark circuits. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | BAST Architecture / don't care Identification / bit flipping reduction / random-pattern resistant fault |
| Paper # | DC2010-11 |
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| Committee | DC |
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| Conference Date | 2010/6/18(1days) |
| Place (in Japanese) | (See Japanese page) |
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| Topics (in Japanese) | (See Japanese page) |
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| Registration To | Dependable Computing (DC) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A test pattern matching method on BAST architecture using don't care identification for the detection of random pattern resistant faults |
| Sub Title (in English) | |
| Keyword(1) | BAST Architecture |
| Keyword(2) | don't care Identification |
| Keyword(3) | bit flipping reduction |
| Keyword(4) | random-pattern resistant fault |
| 1st Author's Name | Yun Chen |
| 1st Author's Affiliation | Graduate School of Industrial Technology, Nihon University() |
| 2nd Author's Name | Toshinori HOSOKAWA |
| 2nd Author's Affiliation | College of Industrial Technology, Nihon University |
| 3rd Author's Name | Masayoshi YOSHIMURA |
| 3rd Author's Affiliation | Graduate School of Information Science and Electrical Engineering, Kyushu University |
| Date | 2010-06-25 |
| Paper # | DC2010-11 |
| Volume (vol) | vol.110 |
| Number (no) | 106 |
| Page | pp.pp.- |
| #Pages | 6 |
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