Presentation 2010-06-18
Hard-wired Shellcode Detection Algorithm : trial implementations on FPGA and ASIC
Hiroki NOGAWA, Fuminori ADACHI, Yasumitsu TSUJINO, Seiji MORIYA, Kazunori SAITO,
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Abstract(in English) Shellcodes are essential parts of remote exploit, and display wide range of varieties (polymorphism). Many researchers have focused on algorithm that enables us to detect shellcodes with polymorphic feature. Though many algorithms for shellcode detection have been proposed, none has been proved to be implemented into hardware and to perform Gbps throughput. We have implemented our shellcode detection algorithm into hardware (FPGA and ASIC), and showed Gbps performance. In this paper, we at first give a short description on our shellcode detection algorithm and the reason why our algorithm is suitable for hardware implementation, and then we show a design summary of our shellcode detection hardware with performance results of our hardware.
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Keyword(in English) shellcode detection / hardware / FPGA / ASIC
Paper # IA2010-15,ICSS2010-15
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Committee IA
Conference Date 2010/6/10(1days)
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Language ENG
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Hard-wired Shellcode Detection Algorithm : trial implementations on FPGA and ASIC
Sub Title (in English)
Keyword(1) shellcode detection
Keyword(2) hardware
Keyword(3) FPGA
Keyword(4) ASIC
1st Author's Name Hiroki NOGAWA
1st Author's Affiliation Secureware Inc.()
2nd Author's Name Fuminori ADACHI
2nd Author's Affiliation Secureware Inc.
3rd Author's Name Yasumitsu TSUJINO
3rd Author's Affiliation Secureware Inc.
4th Author's Name Seiji MORIYA
4th Author's Affiliation Secureware Inc.
5th Author's Name Kazunori SAITO
5th Author's Affiliation Secureware Inc.
Date 2010-06-18
Paper # IA2010-15,ICSS2010-15
Volume (vol) vol.110
Number (no) 78
Page pp.pp.-
#Pages 6
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