| Presentation | 2010-04-13 Accurate Asynchronous Network-on-Chip Simulation Based on Reactive Delay Model Tomoyoshi FUNAZAKI, Naoya ONIZAWA, Atsushi MATSUMOTO, Takahiro HANYU, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | A performance-evaluation simulator, such as a cycle-accurate simulator, is a key tool for exploring appropriate asynchronous Network-on-Chip(NoC)architectures in early stages of VLSI design, but its accuracy is insufficient in practical VLSI implementation. In this paper, a highly accurate performance-evaluation simulator based on a reactive delay model is proposed for implementing an appropriate asynchronous NoC system. While the unit delay between circuit blocks at every pipeline stage is constant in the conventional cycle-accurate simulator, which causes poor accuracy, the unit delay between circuit blocks in the proposed approach is determined independently by its desirable logic function. The use of this "reactive delay" model makes it accurate to simulate asynchronous NoC systems. As a design example, a 16-core asynchronous Spidergon NoC system is simulated by the conventional cycle-accurate and the proposed simulator whose results, such as latency and throughput, are validated with a highly precise transistor-level simulation result. As a result, the proposed simulator achieves almost the same accuracy as one of the transistor-level simulators with the simulation speed comparable to the cycle-accurate simulator. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Network-on-Chip / Asynchronous Circuits / Quasi Delay Insensitive |
| Paper # | CPSY2010-3,DC2010-3 |
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| Conference Information | |
| Committee | DC |
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| Conference Date | 2010/4/6(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Dependable Computing (DC) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Accurate Asynchronous Network-on-Chip Simulation Based on Reactive Delay Model |
| Sub Title (in English) | |
| Keyword(1) | Network-on-Chip |
| Keyword(2) | Asynchronous Circuits |
| Keyword(3) | Quasi Delay Insensitive |
| 1st Author's Name | Tomoyoshi FUNAZAKI |
| 1st Author's Affiliation | Research Institute of Electrical Communication, Tohoku University() |
| 2nd Author's Name | Naoya ONIZAWA |
| 2nd Author's Affiliation | Research Institute of Electrical Communication, Tohoku University |
| 3rd Author's Name | Atsushi MATSUMOTO |
| 3rd Author's Affiliation | Research Institute of Electrical Communication, Tohoku University |
| 4th Author's Name | Takahiro HANYU |
| 4th Author's Affiliation | Research Institute of Electrical Communication, Tohoku University |
| Date | 2010-04-13 |
| Paper # | CPSY2010-3,DC2010-3 |
| Volume (vol) | vol.110 |
| Number (no) | 3 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |