| Presentation | 2010-03-28 A consideration of synthesis methods for easily testable parallel prefix adders Shinichi FUJII, Naofumi TAKAGI, |
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| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Previously, synthesis methods of parallel prefix adders have been proposed. These methods primarily use circuit area and delay constraints during synthesis. Recently, test cost of VLSI chip have increased because VLSI technology has developed to the large-scale and complexity circuit design. Therefore, it is useful that testability is considered for synthesis constraints. In this paper, we consider a synthesis method of testable parallel prefix adders in a small area under delay constraints. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | parallel prefix adders / design for testability / synthesis |
| Paper # | CPSY2009-93,DC2009-90 |
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| Conference Information | |
| Committee | DC |
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| Conference Date | 2010/3/19(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Dependable Computing (DC) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A consideration of synthesis methods for easily testable parallel prefix adders |
| Sub Title (in English) | |
| Keyword(1) | parallel prefix adders |
| Keyword(2) | design for testability |
| Keyword(3) | synthesis |
| 1st Author's Name | Shinichi FUJII |
| 1st Author's Affiliation | Department of Information Engineering, Nagoya University() |
| 2nd Author's Name | Naofumi TAKAGI |
| 2nd Author's Affiliation | Department of Information Engineering, Nagoya University |
| Date | 2010-03-28 |
| Paper # | CPSY2009-93,DC2009-90 |
| Volume (vol) | vol.109 |
| Number (no) | 475 |
| Page | pp.pp.- |
| #Pages | 5 |
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