Presentation 2010-03-28
Development of a URL Filtering System for Ultra-high Speed Networks
Kenji TODA, Mamoru SEKIYAMA, Takuya KUBOTA,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) The FPGA board having two DDR2 ports and six 10GbE ports is developed and implemented hybrid method using hash and binary search. In the system, the filtering of the URL black list of the feasible size is performed at the speed of several tens of Gbps.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) URL Filtering / FPGA / Hash / Binary Search / 10G bit Ethernet
Paper # CPSY2009-92,DC2009-89
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Committee DC
Conference Date 2010/3/19(1days)
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Paper Information
Registration To Dependable Computing (DC)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Development of a URL Filtering System for Ultra-high Speed Networks
Sub Title (in English)
Keyword(1) URL Filtering
Keyword(2) FPGA
Keyword(3) Hash
Keyword(4) Binary Search
Keyword(5) 10G bit Ethernet
1st Author's Name Kenji TODA
1st Author's Affiliation Information Technology Research Institute, National Institute of Advanced Industrial Science and Technology(AIST)()
2nd Author's Name Mamoru SEKIYAMA
2nd Author's Affiliation Information Technology Research Institute, National Institute of Advanced Industrial Science and Technology(AIST)
3rd Author's Name Takuya KUBOTA
3rd Author's Affiliation Information Technology Research Institute, National Institute of Advanced Industrial Science and Technology(AIST)
Date 2010-03-28
Paper # CPSY2009-92,DC2009-89
Volume (vol) vol.109
Number (no) 475
Page pp.pp.-
#Pages 6
Date of Issue