| Presentation | 2010-03-28 Design of Look-Ahead Router for Low Latency Real-Time On-Chip Networks Takuma KOGO, Nobuyuki YAMASAKI, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Scheduling algorithms are very important to realize a real-time system by using large-scale chip multiprocessors(CMPs). Most real-time scheduling algorithms assume preemption and worst-case execution time. It is challenging topic to handle these requirements on Networks-on-Chip(NoC)which interconnects each core in large-scale CMP, because some on-chip constraints exist including amount of hardware and energy. Preemption mechanism may decrease throughput and increase latency. As result, application performance may fall down. This paper proposes a look-ahead on-chip router for a preemptable NoC. Proposed scheme reduces a number of pipeline stages and improves latency. We implemented the look-ahead on-chip router by using HDL and evaluated it by using synthetic traffics. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Real-Time / Multi-core / Many-core / On-chip Networks / Networks-on-Chip(NoC) / Low Latency |
| Paper # | CPSY2009-89,DC2009-86 |
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| Conference Information | |
| Committee | DC |
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| Conference Date | 2010/3/19(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Dependable Computing (DC) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Design of Look-Ahead Router for Low Latency Real-Time On-Chip Networks |
| Sub Title (in English) | |
| Keyword(1) | Real-Time |
| Keyword(2) | Multi-core |
| Keyword(3) | Many-core |
| Keyword(4) | On-chip Networks |
| Keyword(5) | Networks-on-Chip(NoC) |
| Keyword(6) | Low Latency |
| 1st Author's Name | Takuma KOGO |
| 1st Author's Affiliation | Department of Computer Science, Graduate School of Science and Technology, Keio University() |
| 2nd Author's Name | Nobuyuki YAMASAKI |
| 2nd Author's Affiliation | Department of Computer Science, Graduate School of Science and Technology, Keio University |
| Date | 2010-03-28 |
| Paper # | CPSY2009-89,DC2009-86 |
| Volume (vol) | vol.109 |
| Number (no) | 475 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |