Presentation 2010-03-27
A Topology Decision Approach of IP Cores for Throughput Improvement of Application Specific NoC System
Hiroshi UCHIKOSHI, Makoto SUGIHARA,
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Abstract(in English) The continuous effort in shrinking the size of a transistor causes a wire delay to increase relatively faster than a gate delay. On-chip communication will be a major factor to determine the performance of a computer system. Network-on-Chip is one of a communication architecture that interconnect with shortly link. This paper proposes a design technique for embedded systems which uses a regular network topology as a communication topology and automatically maps IP cores onto the topology so that the high communication throughput is achieved. Our design technique formulate communication throughput, then decide an IP core topology that maximize communication throughput. We also experimentally confirmed that out design technique achieved high communication throughput.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Network-on-Chip / Embedded system / throughput improvement / IP core / topology / optimization
Paper # CPSY2009-88,DC2009-85
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Committee DC
Conference Date 2010/3/19(1days)
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Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A Topology Decision Approach of IP Cores for Throughput Improvement of Application Specific NoC System
Sub Title (in English)
Keyword(1) Network-on-Chip
Keyword(2) Embedded system
Keyword(3) throughput improvement
Keyword(4) IP core
Keyword(5) topology
Keyword(6) optimization
1st Author's Name Hiroshi UCHIKOSHI
1st Author's Affiliation Toyohashi University of Technology()
2nd Author's Name Makoto SUGIHARA
2nd Author's Affiliation Toyohashi University of Technology:Japan Science and Technology Agency, JST
Date 2010-03-27
Paper # CPSY2009-88,DC2009-85
Volume (vol) vol.109
Number (no) 475
Page pp.pp.-
#Pages 6
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