Presentation 2010-03-27
Quantitative Evaluation of Task-Switching Overhead in Cache Memory
Mitsunori SERIZAWA, Makoto SUGIHARA,
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Abstract(in English) In the state-of-the-art computer systems trend, it is indispensable to have cache memory for high-speed processing, and multitask processing which executes multiple tasks by switching. With multitasking, it is necessary for data of a preceding task in a cache memory to evacuate to a main memory at the time of task switching. In this research, based on the idea that the performance of processors will be improved by decreasing performance overhead, dirty lines in cache memories, which are the cause of performance overhead, are to be focused. The quantitative evaluation of performance overhead caused by the dirty lines expelled by task switching was conducted. As a result, it was found out that the performance overhead was influenced by the programs, the time slices and the execution cycles increased 37 percent compared to the cases where task switching did not occur.
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Keyword(in English) cache memory / task switching / dirty line / performance overhead
Paper # CPSY2009-85,DC2009-82
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Committee DC
Conference Date 2010/3/19(1days)
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Registration To Dependable Computing (DC)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Quantitative Evaluation of Task-Switching Overhead in Cache Memory
Sub Title (in English)
Keyword(1) cache memory
Keyword(2) task switching
Keyword(3) dirty line
Keyword(4) performance overhead
1st Author's Name Mitsunori SERIZAWA
1st Author's Affiliation Toyohashi University of Technology()
2nd Author's Name Makoto SUGIHARA
2nd Author's Affiliation Toyohashi University of Technology:Japan Science and Technology Agency, JST
Date 2010-03-27
Paper # CPSY2009-85,DC2009-82
Volume (vol) vol.109
Number (no) 475
Page pp.pp.-
#Pages 6
Date of Issue