Presentation 2010-02-15
Study on a Test Generation Method for Transition Fault Using Multi Cycle Capture Test
Hiroshi OGAWA, Toshinori HOSOKAWA, Masayoshi YOSHIMURA, Kouji YAMAZAKI,
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Abstract(in English) Overtesting induces unnecessary yield loss. Untestable faults have no effect on normal functions of circuits. However, in scan testing, untestable faults may be detected through scan chains. Detected untestable faults cause overtesting. Untestable faults consist of uncontrollable faults, unobservable faults, and uncontrollable and unobservable faults. Uncontrollable faults may be detected under invalid states through scan chains by shift-in operations. Unobservable faults cannot be observed at primary outputs, but their effects may be propagated to scan flip-flops. Thus, unobservable faults may be detected through scan chains by shift-out operations. Several methods to reduce the number of detected untestable faults were recently proposed. These methods identify invalid states and generate test patterns avoiding invalid states. As the result, the number of detected uncontrollable faults was reduced. However, they cannot reduce the number of detected unobservable faults. In this paper, both uncontrollable and unobservable faults are identified using a multi-cycle capture test generation method. We evaluate the relationship between the numbers of untestable faults and the fault excitation time for ISCAS'89 benchmark circuits, and also evaluate factors that untestable faults are identified.
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Keyword(in English) transition faults / over testing / time expansion models / multi-cycle capture test / untestable faults
Paper # DC2009-67
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Committee DC
Conference Date 2010/2/8(1days)
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Registration To Dependable Computing (DC)
Language JPN
Title (in Japanese) (See Japanese page)
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Title (in English) Study on a Test Generation Method for Transition Fault Using Multi Cycle Capture Test
Sub Title (in English)
Keyword(1) transition faults
Keyword(2) over testing
Keyword(3) time expansion models
Keyword(4) multi-cycle capture test
Keyword(5) untestable faults
1st Author's Name Hiroshi OGAWA
1st Author's Affiliation Graduate School of Industrial Technology, Nihon University()
2nd Author's Name Toshinori HOSOKAWA
2nd Author's Affiliation College of Industrial Technology, Nihon University
3rd Author's Name Masayoshi YOSHIMURA
3rd Author's Affiliation Graduate School of Information Science and Electrical Engineering, Kyushu University
4th Author's Name Kouji YAMAZAKI
4th Author's Affiliation School of Information and Communication, Meiji University
Date 2010-02-15
Paper # DC2009-67
Volume (vol) vol.109
Number (no) 416
Page pp.pp.-
#Pages 6
Date of Issue