| Presentation | 2009-12-11 Enumeration and Synthesis of Shift Register Equivalents for Secure Scan Design Katsuya FUJIWARA, Hideo FUJIWARA, Hideo TAMAMOTO, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Although there exists an inherent contradiction between security and testability for digital circuits, it is important to find an efficient design-for-testability methodology that satisfies both security and testability. The authors reported a secure and testable scan design approach by using extended shift registers that are functionally equivalent but not structurally equivalent to shift registers. The security level of the secure and testable scan architecture based on those shift register equivalents is determined by the probability that an attacker can identify the configuration of the shift register equivalent used in the circuit, and hence the attack probability approximates to the reciprocal of the cardinality of the class of shift register equivalents. In this paper, we clarify the cardinality of each class of shift register equivalents from several linear structure circuits, and present the lower and upper bound of the cardinality of the whole class of shift register equivalents. We also consider the enumeration problem of shift register equivalents and the synthesis problem of desired shift register equivalents. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Design for Testability / Secure Scan / Shift Register / Functional Equivalence / Enumeration / Synthesis |
| Paper # | DC2009-58 |
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| Conference Information | |
| Committee | DC |
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| Conference Date | 2009/12/4(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Dependable Computing (DC) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Enumeration and Synthesis of Shift Register Equivalents for Secure Scan Design |
| Sub Title (in English) | |
| Keyword(1) | Design for Testability |
| Keyword(2) | Secure Scan |
| Keyword(3) | Shift Register |
| Keyword(4) | Functional Equivalence |
| Keyword(5) | Enumeration |
| Keyword(6) | Synthesis |
| 1st Author's Name | Katsuya FUJIWARA |
| 1st Author's Affiliation | Faculty of Engineering and Resource Science, Akita University() |
| 2nd Author's Name | Hideo FUJIWARA |
| 2nd Author's Affiliation | Graduate School of Information Science, Nara Institute of Science and Technology |
| 3rd Author's Name | Hideo TAMAMOTO |
| 3rd Author's Affiliation | Faculty of Engineering and Resource Science, Akita University |
| Date | 2009-12-11 |
| Paper # | DC2009-58 |
| Volume (vol) | vol.109 |
| Number (no) | 334 |
| Page | pp.pp.- |
| #Pages | 6 |
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