| Presentation | 2009-12-11 Note on Programmable On-Product Clock Generation(OPCG)Circuitry for Low Power Aware Delay Test Anis Uzzaman, Brion Keller, Tom Snethen, Kazuhiko Iwasaki, Masayuki Arai, |
|---|---|
| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | This paper describes how we provide a mean for dealing with the programmable aspects of on-product clock generation(OPCG)for use during ATPG and how that can also help with low power delay test. The system described in this paper automatically generates mode initialization sequence, setup sequence, test sequence and others and enables low power aware delay test when faster on product clocks are present on board. This system has successfully been used to process delay test for ASIC chips even with 22 PLLs on board. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | OPCG / Delay Test / Low Power / EDA / ASIC / ATE |
| Paper # | DC2009-57 |
| Date of Issue |
| Conference Information | |
| Committee | DC |
|---|---|
| Conference Date | 2009/12/4(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Dependable Computing (DC) |
|---|---|
| Language | ENG |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Note on Programmable On-Product Clock Generation(OPCG)Circuitry for Low Power Aware Delay Test |
| Sub Title (in English) | |
| Keyword(1) | OPCG |
| Keyword(2) | Delay Test |
| Keyword(3) | Low Power |
| Keyword(4) | EDA |
| Keyword(5) | ASIC |
| Keyword(6) | ATE |
| 1st Author's Name | Anis Uzzaman |
| 1st Author's Affiliation | Cadence Design Systems Inc.:Faculty of System Design, Tokyo Metropolitan University() |
| 2nd Author's Name | Brion Keller |
| 2nd Author's Affiliation | Cadence Design Systems Inc. |
| 3rd Author's Name | Tom Snethen |
| 3rd Author's Affiliation | Cadence Design Systems Inc. |
| 4th Author's Name | Kazuhiko Iwasaki |
| 4th Author's Affiliation | Faculty of System Design, Tokyo Metropolitan University |
| 5th Author's Name | Masayuki Arai |
| 5th Author's Affiliation | Faculty of System Design, Tokyo Metropolitan University |
| Date | 2009-12-11 |
| Paper # | DC2009-57 |
| Volume (vol) | vol.109 |
| Number (no) | 334 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |