Presentation 2009-12-04
Automatic Generation of Design-Specific Cell Libraries
Hiroaki YOSHIDA, Masahiro FUJITA,
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Abstract(in English) In spite of the significant advances of computer-aided design tools for LSIs over the decades, there has been a large performance gap between ASICs and custom LSIs. One of the major limiting factors is a use of generic-purpose cell libraries. In this paper, we propose an automated methodology for generating a cell library specific to a given circuit and design constraints. A case study using a benchmark circuit demonstrates that using the design-specific cell libraries, the area-delay tradeoff curve is shifted to the left-bottom from that using a typical cell library. This result shows that the proposed methodology can achieve an intrinsic improvement.
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Keyword(in English) Standard cell libraries / high-performance design / logic synthesis / transistor sizing
Paper # VLD2009-67,DC2009-54
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Committee DC
Conference Date 2009/11/25(1days)
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Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Automatic Generation of Design-Specific Cell Libraries
Sub Title (in English)
Keyword(1) Standard cell libraries
Keyword(2) high-performance design
Keyword(3) logic synthesis
Keyword(4) transistor sizing
1st Author's Name Hiroaki YOSHIDA
1st Author's Affiliation VLSI Design and Education Center(VDEC), University of Tokyo:CREST, Japan Science and Technology Agency()
2nd Author's Name Masahiro FUJITA
2nd Author's Affiliation VLSI Design and Education Center(VDEC), University of Tokyo:CREST, Japan Science and Technology Agency
Date 2009-12-04
Paper # VLD2009-67,DC2009-54
Volume (vol) vol.109
Number (no) 316
Page pp.pp.-
#Pages 6
Date of Issue