| Presentation | 2009-12-04 Evaluation of Energy Consumption on Multipliers Using the Sum of Operands Hirotaka KAWASHIMA, Naofumi TAKAGI, |
|---|---|
| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | We evaluate dynamic energy consumption of multipliers using the sum of operands we have proposed before. The multipliers using sum of operands reduce the number of partial product bits efficiently, and are designed in the smaller number of circuit elements than existing multipliers. The dynamic energy consumption can be reduced by reducing the number of signal transitions. Reducing the number of circuit elements is one of the method of reducing the signal transitions. On the other hand, our previous work shows that energy consumption on the parallel multipliers depends on not only the number of circuit elements but also circuit construction. We evaluate energy consumption of the multipliers composed of the smaller number of circuit elements, and show how reducing the circuit elements effects reducing the dynamic energy consumption. Simulation results show that the energy consumption of the Wallace multipliers is less than the multipliers using the sum of operands. It is shown that reducing the number of circuit elements does not necessarily lead to reducing the dynamic energy consumption. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | parallel multiplier / energy consumption / the number of circuit elements |
| Paper # | VLD2009-66,DC2009-53 |
| Date of Issue |
| Conference Information | |
| Committee | DC |
|---|---|
| Conference Date | 2009/11/25(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Dependable Computing (DC) |
|---|---|
| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Evaluation of Energy Consumption on Multipliers Using the Sum of Operands |
| Sub Title (in English) | |
| Keyword(1) | parallel multiplier |
| Keyword(2) | energy consumption |
| Keyword(3) | the number of circuit elements |
| 1st Author's Name | Hirotaka KAWASHIMA |
| 1st Author's Affiliation | Department of Information Engineering, Graduate School of Information Science, Nagoya University() |
| 2nd Author's Name | Naofumi TAKAGI |
| 2nd Author's Affiliation | Department of Information Engineering, Graduate School of Information Science, Nagoya University |
| Date | 2009-12-04 |
| Paper # | VLD2009-66,DC2009-53 |
| Volume (vol) | vol.109 |
| Number (no) | 316 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |