Presentation 2009-12-04
A Path Selection Method of Delay Test for Transistor Aging
Mitsumasa NODA, Seiji KAJIHARA, Yasuo SATO, Kohei MIYASE, Xiaoqing WEN, Takaya MIURA,
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Abstract(in English) With the advanced VLSI process technology, it is important for reliability of VLSIs to deal with faults caused by aging. The speed of aging depends on not only the function of the circuit but also environment where the circuit is used. Hence detection of aging that would make a failure prefers to test on the field after shipping the VLSIs. This paper presents a method for selecting paths to be tested for delay degradation caused by NBTI under BIST-based self testing.
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Keyword(in English) Aging / Negative Bias Temperature Instability / Delay Fault / Path selection
Paper # VLD2009-65,DC2009-52
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Committee DC
Conference Date 2009/11/25(1days)
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Paper Information
Registration To Dependable Computing (DC)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A Path Selection Method of Delay Test for Transistor Aging
Sub Title (in English)
Keyword(1) Aging
Keyword(2) Negative Bias Temperature Instability
Keyword(3) Delay Fault
Keyword(4) Path selection
1st Author's Name Mitsumasa NODA
1st Author's Affiliation Kyushu Institute of Technology()
2nd Author's Name Seiji KAJIHARA
2nd Author's Affiliation Kyushu Institute of Technology:JST CREST
3rd Author's Name Yasuo SATO
3rd Author's Affiliation Kyushu Institute of Technology:JST CREST
4th Author's Name Kohei MIYASE
4th Author's Affiliation Kyushu Institute of Technology:JST CREST
5th Author's Name Xiaoqing WEN
5th Author's Affiliation Kyushu Institute of Technology:JST CREST
6th Author's Name Takaya MIURA
6th Author's Affiliation Faculty of System Design, Tokyo Metropolitan University:JST CREST
Date 2009-12-04
Paper # VLD2009-65,DC2009-52
Volume (vol) vol.109
Number (no) 316
Page pp.pp.-
#Pages 6
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