| Presentation | 2009-12-04 A secure design for testability of RSA encryption circuits Teppei HAYAKAWA, Toshinori HOSOKAWA, Masayoshi YOSHIMURA, |
|---|---|
| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Full scan designs are popular ones for testability. However, the application of full scan designs for encryption circuits causes leaks of secret informations. In this paper, we propose a design for testability(DFT)method to increase fault coverage maintaining security for RSA encryption circuits. First, partial scan design that critical registers including secret informations are not replaced with scan registers is applied to the circuits. Second, XOR trees are inserted into the circuits to increase the observabilities. XOR tree prevent secret informations from leaking out by compacting several observation points to one scan register. Finally, control points are inserted into the circuits to increase the contrallabitlities. Security and testability are compatible on scan designs by applying the proposed DFT method. Experimental results for RSA encryption circuits show that the proposed DFT method can achieve the almost same high fault efficiency as full scan design maintaining. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | RSA encryption circuits / scan design / security / XOR trees / test points |
| Paper # | VLD2009-63,DC2009-50 |
| Date of Issue |
| Conference Information | |
| Committee | DC |
|---|---|
| Conference Date | 2009/11/25(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Dependable Computing (DC) |
|---|---|
| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A secure design for testability of RSA encryption circuits |
| Sub Title (in English) | |
| Keyword(1) | RSA encryption circuits |
| Keyword(2) | scan design |
| Keyword(3) | security |
| Keyword(4) | XOR trees |
| Keyword(5) | test points |
| 1st Author's Name | Teppei HAYAKAWA |
| 1st Author's Affiliation | Graduate School of Industrial Technology, Nihon University() |
| 2nd Author's Name | Toshinori HOSOKAWA |
| 2nd Author's Affiliation | College of Industrial Technology, Nihon University |
| 3rd Author's Name | Masayoshi YOSHIMURA |
| 3rd Author's Affiliation | Graduate School of Information Science and Electrical Engineering, Kyushu University |
| Date | 2009-12-04 |
| Paper # | VLD2009-63,DC2009-50 |
| Volume (vol) | vol.109 |
| Number (no) | 316 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |