Presentation 2009-12-04
Analysis of Layout Structure Dependency on Distance/Space Variation for MOS Transistors
Yuichi SADOHIRA, Shigetoshi NAKATAKE,
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Abstract(in English) In this paper, we investigate the dependency of layout structures such as diffusion sharing/isolation and gate division on MOS transistor characteristics against the variation caused by manufacturing. We developed TEG chips on 90nm manufacturing process and evaluated them for the investigation. Each chip is composed of 7×7 units, various sizes and layouts of MOS transistors are embedded in each of units. We measured Vth of each transistors and analyzed them. In the analysis, we identified the space-dependent components and distance-dependent components from the variation values of the measured Vth.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) MOS Transistor / Manufacturing Variation / Distance-Dependent Variation / Space-Dependent Variation / Layout-Structure-Dependency
Paper # VLD2009-61,DC2009-48
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Committee DC
Conference Date 2009/11/25(1days)
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Registration To Dependable Computing (DC)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Analysis of Layout Structure Dependency on Distance/Space Variation for MOS Transistors
Sub Title (in English)
Keyword(1) MOS Transistor
Keyword(2) Manufacturing Variation
Keyword(3) Distance-Dependent Variation
Keyword(4) Space-Dependent Variation
Keyword(5) Layout-Structure-Dependency
1st Author's Name Yuichi SADOHIRA
1st Author's Affiliation School of Environmental Engineering, The University of Kitakyushu()
2nd Author's Name Shigetoshi NAKATAKE
2nd Author's Affiliation School of Environmental Engineering, The University of Kitakyushu
Date 2009-12-04
Paper # VLD2009-61,DC2009-48
Volume (vol) vol.109
Number (no) 316
Page pp.pp.-
#Pages 6
Date of Issue