| Presentation | 2009-12-04 Increasing Yield Using Partially-Programmable Circuits Shigeru YAMASHITA, Hiroaki YOSHIDA, Masahiro FUJITA, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | This paper proposes to use Partially-Programmable Circuits(PPCs)which are obtained from conventional logic circuits by replacing their sub-circuits with LUTs. If a connection in a PPC becomes redundant by changing the functionality of some LUTs, the connection is considered to be robust to defects because even if there are some defects at the connection, the circuit works properly by changing the functionality of some LUTs appropriately. To increase the number of such robust connections, we add some redundant connections to LUTs. We find such redundant connection by using functional flexibility represented by SPFDs and/or CSPFs. From the result of our preliminary experiments, we consider our approach is promising. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | yield / LUT / Partially-Programmable Circuit(PPC) / SPFD |
| Paper # | VLD2009-59,DC2009-46 |
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| Conference Information | |
| Committee | DC |
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| Conference Date | 2009/11/25(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Dependable Computing (DC) |
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| Language | ENG |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Increasing Yield Using Partially-Programmable Circuits |
| Sub Title (in English) | |
| Keyword(1) | yield |
| Keyword(2) | LUT |
| Keyword(3) | Partially-Programmable Circuit(PPC) |
| Keyword(4) | SPFD |
| 1st Author's Name | Shigeru YAMASHITA |
| 1st Author's Affiliation | College of Information Science and Engineering, Ritsumeikan University() |
| 2nd Author's Name | Hiroaki YOSHIDA |
| 2nd Author's Affiliation | VLSI Design and Education Center(VDEC), University of Tokyo |
| 3rd Author's Name | Masahiro FUJITA |
| 3rd Author's Affiliation | VLSI Design and Education Center(VDEC), University of Tokyo |
| Date | 2009-12-04 |
| Paper # | VLD2009-59,DC2009-46 |
| Volume (vol) | vol.109 |
| Number (no) | 316 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |