Presentation 2009-12-03
A Yield Model with Testability and Repairability
Yujiro AMANO, Yuki YOSHIKAWA, Hideyuki ICHIHARA, Tomoo INOUE,
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Abstract(in English) For deep-submicron technology, the increase in transitive and permanent faults of LSIs is a critical problem due to the considerable loss of production yield and the large increase in defect level. In this paper, we focus on repairable and testable designs of logic circuits, and propose a new yield model, which represents the impacts of these designs on production yield and defect level. The proposed model is applied to three testable designs and one repairable design to clarify the relationship between the designs and the production cost / reliability of LSIs.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) yield / defect level / design-for-testability / repairable design
Paper # VLD2009-54,DC2009-41
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Committee DC
Conference Date 2009/11/25(1days)
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Registration To Dependable Computing (DC)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A Yield Model with Testability and Repairability
Sub Title (in English)
Keyword(1) yield
Keyword(2) defect level
Keyword(3) design-for-testability
Keyword(4) repairable design
1st Author's Name Yujiro AMANO
1st Author's Affiliation Graduate School of Information Sciences, Hiroshima City University()
2nd Author's Name Yuki YOSHIKAWA
2nd Author's Affiliation Graduate School of Information Sciences, Hiroshima City University
3rd Author's Name Hideyuki ICHIHARA
3rd Author's Affiliation Graduate School of Information Sciences, Hiroshima City University
4th Author's Name Tomoo INOUE
4th Author's Affiliation Graduate School of Information Sciences, Hiroshima City University
Date 2009-12-03
Paper # VLD2009-54,DC2009-41
Volume (vol) vol.109
Number (no) 316
Page pp.pp.-
#Pages 6
Date of Issue