Presentation 2009-12-02
Two-level Cache Simulation with L2 Unified Cache for Embedded Applications
Yuta KOBAYASHI, Nozomu TOGAWA, Masao YANAGISAWA, Tatsuo OHTSUKI,
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Abstract(in English) In this paper, we propose a two-level cache simulation method with L2 unified cache for embedded applications. It simulates L1 instruction cache, L1 data cache and L2 unified cache accurately in short period of time, by repeating simulation for L1/L2 instruction(data) cache several times. Additionally, by using several cache properties we can obtain the number of cache hits/misses without simulating several cache configurations. Our proposed approach totally runs a maximum of 3662.93 times faster than that of the conventional exhaustive approach.
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Keyword(in English) cache / unified cache / cache simulation / cache optimization / embedded system
Paper # VLD2009-47,DC2009-34
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Committee DC
Conference Date 2009/11/25(1days)
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Registration To Dependable Computing (DC)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Two-level Cache Simulation with L2 Unified Cache for Embedded Applications
Sub Title (in English)
Keyword(1) cache
Keyword(2) unified cache
Keyword(3) cache simulation
Keyword(4) cache optimization
Keyword(5) embedded system
1st Author's Name Yuta KOBAYASHI
1st Author's Affiliation Dept. of Computer Science and Engineering, Waseda University()
2nd Author's Name Nozomu TOGAWA
2nd Author's Affiliation Dept. of Computer Science and Engineering, Waseda University
3rd Author's Name Masao YANAGISAWA
3rd Author's Affiliation Dept. of Computer Science and Engineering, Waseda University
4th Author's Name Tatsuo OHTSUKI
4th Author's Affiliation Dept. of Computer Science and Engineering, Waseda University
Date 2009-12-02
Paper # VLD2009-47,DC2009-34
Volume (vol) vol.109
Number (no) 316
Page pp.pp.-
#Pages 6
Date of Issue