Presentation 2009-12-02
Evaluation of Hardware/Software Partitioning Method with Consideration of Timing
Junya Matsunaga, Michiaki Muraoka,
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Abstract(in English) The optimal hardware/software partitioning is an important issue in the system level design. In the conventional design, it was difficult to partition an architecture with consideration of the execution cycle count of the software. In this research, a hardware/software partitioning method and a software parallelization method based on C description with consideration of the execution cycle count of the software are proposed. After this method was applied to the encryption algorithm AES, the software parallelization method reduces the execution cycle count by almost 60 percent of the bottleneck part of the software.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Hardware/Software co-design / co-simulation / Hardware/Software Partitioning / ESL
Paper # VLD2009-46,DC2009-33
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Committee DC
Conference Date 2009/11/25(1days)
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Registration To Dependable Computing (DC)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Evaluation of Hardware/Software Partitioning Method with Consideration of Timing
Sub Title (in English)
Keyword(1) Hardware/Software co-design
Keyword(2) co-simulation
Keyword(3) Hardware/Software Partitioning
Keyword(4) ESL
1st Author's Name Junya Matsunaga
1st Author's Affiliation Information Science Division, Graduate School of Science Kochi University()
2nd Author's Name Michiaki Muraoka
2nd Author's Affiliation Information Science Division, Graduate School of Science Kochi University
Date 2009-12-02
Paper # VLD2009-46,DC2009-33
Volume (vol) vol.109
Number (no) 316
Page pp.pp.-
#Pages 6
Date of Issue