Presentation 2009-10-20
Access Time Measurement of 64kb Josephson/CMOS Hybrid Memories using SFQ Time-to-Digital Converter
Yuji OKAMOTO, Heejoung PARK, Hyunjoo JIN, Kenta YAGUCHI, Yuki YAMANASHI, Nobuyuki YOSHIKAWA,
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Abstract(in English) We have been developing a Josephson/CMOS hybrid memory, which enables the sub-nanosecond access time to overcome a memory bottleneck in RSFQ digital systems. In our previous study, we obtained the access time of about 1.2ns in the 16kb hybrid memory system using a 0.35μm CMOS process. But, we faced with a problem of double peaks in histograms. In this study, we designed a 64kb hybrid memory system using a 0.18μm CMOS process. We consider that a reason of the double peak problem is due to the parasitic capacitance at the bonding pad of the Josephson and CMOS chips. We measured the access time using the Josephson and CMOS chips with reduced parasitic capacitance, and obtained the access time of about 1.4ns in the 64kb hybrid memory system.
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Keyword(in English) Superconducting integrated circuits / SFQ circuits / Hybrid memory / Access time / Parasitic capacitance
Paper # SCE2009-21
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Conference Information
Committee SCE
Conference Date 2009/10/13(1days)
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Registration To Superconductive Electronics (SCE)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Access Time Measurement of 64kb Josephson/CMOS Hybrid Memories using SFQ Time-to-Digital Converter
Sub Title (in English)
Keyword(1) Superconducting integrated circuits
Keyword(2) SFQ circuits
Keyword(3) Hybrid memory
Keyword(4) Access time
Keyword(5) Parasitic capacitance
1st Author's Name Yuji OKAMOTO
1st Author's Affiliation Department of Electrical and Computer Engineering, Yokohama National University()
2nd Author's Name Heejoung PARK
2nd Author's Affiliation Department of Electrical and Computer Engineering, Yokohama National University
3rd Author's Name Hyunjoo JIN
3rd Author's Affiliation Department of Electrical and Computer Engineering, Yokohama National University
4th Author's Name Kenta YAGUCHI
4th Author's Affiliation Department of Electrical and Computer Engineering, Yokohama National University
5th Author's Name Yuki YAMANASHI
5th Author's Affiliation Department of Electrical and Computer Engineering, Yokohama National University
6th Author's Name Nobuyuki YOSHIKAWA
6th Author's Affiliation Department of Electrical and Computer Engineering, Yokohama National University
Date 2009-10-20
Paper # SCE2009-21
Volume (vol) vol.109
Number (no) 236
Page pp.pp.-
#Pages 5
Date of Issue