| Presentation | 2009-10-20 Design of SFQ Floating-Point Units Using Nb Advanced Process Toshiki Kainuma, Yasuhiro Shimamura, Fumishige Miyaoka, Yuki Yamanashi, Nobuyuki Yoshikawa, Akira Fujimaki, Naofumi Takagi, Kazuyoshi Takagi, |
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| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | We are developing a large-scale reconfigurable data-path (LSRDP) based on the single-flux-quantum (SFQ) circuits, which will be a fundamental technology for future petaflops-scale computing systems. The LSRDP is composed of a large number of floating-point units (FPUs) each of which is connected by reconfigurable routing networks. In the LSRDP, reputation loops in the source program are directly mapped to the LSRDP. The main advantage of the LSRDP is the reduction of the memory wall problem in the high-performance computing system. A memory access rate is considerably reduced, because the data are directly transferred between FPUs in the LSRDP without memory accesses. Recently, the ISTEC Nb 10kA/cm^2 advanced process (ADP), which realizes SFQ circuits with two times faster operating speed than that of the conventional fabrication process has been developed. The final goal of the SFQ processor project with the LSRDP is to demonstrate a 50GHz high-speed operation of SFQ LSRDP Systems. In this paper, we will show the design of component circuits of SFQ floating-point adders and multipliers using the ADP cell library. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | SFQ circuit / Nb process / Floating-point unit / Floating-point adder / Floating-point multiplier / Reconfigurable data-path |
| Paper # | SCE2009-19 |
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| Conference Information | |
| Committee | SCE |
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| Conference Date | 2009/10/13(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Superconductive Electronics (SCE) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Design of SFQ Floating-Point Units Using Nb Advanced Process |
| Sub Title (in English) | |
| Keyword(1) | SFQ circuit |
| Keyword(2) | Nb process |
| Keyword(3) | Floating-point unit |
| Keyword(4) | Floating-point adder |
| Keyword(5) | Floating-point multiplier |
| Keyword(6) | Reconfigurable data-path |
| 1st Author's Name | Toshiki Kainuma |
| 1st Author's Affiliation | Department of Electrical and Computer Engineering, Yokohama National University() |
| 2nd Author's Name | Yasuhiro Shimamura |
| 2nd Author's Affiliation | Department of Electrical and Computer Engineering, Yokohama National University |
| 3rd Author's Name | Fumishige Miyaoka |
| 3rd Author's Affiliation | Department of Electrical and Computer Engineering, Yokohama National University |
| 4th Author's Name | Yuki Yamanashi |
| 4th Author's Affiliation | Department of Electrical and Computer Engineering, Yokohama National University |
| 5th Author's Name | Nobuyuki Yoshikawa |
| 5th Author's Affiliation | Department of Electrical and Computer Engineering, Yokohama National University |
| 6th Author's Name | Akira Fujimaki |
| 6th Author's Affiliation | Department of Quantum Engineering, Nagoya University |
| 7th Author's Name | Naofumi Takagi |
| 7th Author's Affiliation | Department of Information Engineering, Nagoya University |
| 8th Author's Name | Kazuyoshi Takagi |
| 8th Author's Affiliation | Department of Information Engineering, Nagoya University |
| Date | 2009-10-20 |
| Paper # | SCE2009-19 |
| Volume (vol) | vol.109 |
| Number (no) | 236 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |