Presentation 2009-10-20
A Clock Line for a Large Scale Reconfigurable Data Paths Processor
Irina KATAEVA, Hiroyuki AKAIKE, Akira FUJIMAKI,
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Abstract(in English) Clocking of the large scale SFQ circuits is a major issue due to accumulated jitter and clock skew that grow with the increase of the clock line length. We have considered two different clocking schemes, linear and tree, for employment in the SFQ Reconfigurable Data Paths processor (SFQ-RDP). The impact of the accumulated jitter on the clock frequency has been estimated and a synchronization scheme proposed.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) SFQ / Reconfigurable Data Paths processor / clock synchronization / jitter
Paper # SCE2009-18
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Conference Information
Committee SCE
Conference Date 2009/10/13(1days)
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Registration To Superconductive Electronics (SCE)
Language ENG
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A Clock Line for a Large Scale Reconfigurable Data Paths Processor
Sub Title (in English)
Keyword(1) SFQ
Keyword(2) Reconfigurable Data Paths processor
Keyword(3) clock synchronization
Keyword(4) jitter
1st Author's Name Irina KATAEVA
1st Author's Affiliation Department of Quantum Engineering, Nagoya University:CREST-JST()
2nd Author's Name Hiroyuki AKAIKE
2nd Author's Affiliation Department of Quantum Engineering, Nagoya University:CREST-JST
3rd Author's Name Akira FUJIMAKI
3rd Author's Affiliation Department of Quantum Engineering, Nagoya University:CREST-JST
Date 2009-10-20
Paper # SCE2009-18
Volume (vol) vol.109
Number (no) 236
Page pp.pp.-
#Pages 5
Date of Issue