| Presentation | 2009-10-20 A Logic Design Verification Method for SFQ Circuits Considering Pipeline Processing Behavior Motoki SATO, Masamitsu TANAKA, Kazuyoshi TAKAGI, Naofumi TAKAGI, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | We propose a verification method of pipeline processing behavior of SFQ circuits. SFQ logic circuits work synchronously at each level of logic gates by feeding the clock signal to each gate. In other words, SFQ logic circuits take pipelined structure at each level of logic gates. Therefore, SFQ circuits must be designed to implement the required functionality, while satisfying the pipeline timing requirements. The verification method proposed in this paper consists of two phases. First, we verify whether the pipeline timing of the circuits is correct. We check whether the data pulse arrives in one clock cycle at each gate in each level from the primary inputs to the primary outputs of the circuit. Next, we verify whether the logic sequence of the circuits as a whole satisfies the specification. We extract sequential logical expression from the designed circuit, and check equivalence of it and sequential logical expression given as a specification. We have applied the proposed method to the 1-bit cell of a systolic multiplier and confirmed that our method is effective. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Superconductive Device / Single Flux Quantum logic circuit / timing analysis / pipeline processing behavior |
| Paper # | SCE2009-17 |
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| Conference Information | |
| Committee | SCE |
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| Conference Date | 2009/10/13(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Registration To | Superconductive Electronics (SCE) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Logic Design Verification Method for SFQ Circuits Considering Pipeline Processing Behavior |
| Sub Title (in English) | |
| Keyword(1) | Superconductive Device |
| Keyword(2) | Single Flux Quantum logic circuit |
| Keyword(3) | timing analysis |
| Keyword(4) | pipeline processing behavior |
| 1st Author's Name | Motoki SATO |
| 1st Author's Affiliation | Nagoya University() |
| 2nd Author's Name | Masamitsu TANAKA |
| 2nd Author's Affiliation | Nagoya University |
| 3rd Author's Name | Kazuyoshi TAKAGI |
| 3rd Author's Affiliation | Nagoya University |
| 4th Author's Name | Naofumi TAKAGI |
| 4th Author's Affiliation | Nagoya University |
| Date | 2009-10-20 |
| Paper # | SCE2009-17 |
| Volume (vol) | vol.109 |
| Number (no) | 236 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |