Presentation | 2009-07-17 Study of stacked NAND type MRAM for universal memory Shoto TAMAI, Shigeyoshi WATANABE, |
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PDF Download Page | PDF download Page Link |
Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | Study of stacked NAND type MRAM for universal memory has been described. Memory cell using surrounded write bit line which enable to use conventional write operation with magnetic field and small cell area of 9F^2 have been newly developed. Furthermore, optimized bias voltage scheme for the gate of selected and path memory cell has been adopted. Using these technology large stacked number of 64 more than that of flash memory and fast read time of less than 60ns have been realized. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | Non-volatile / MRAM / spin transistor / stacked NAND structure / universal memory |
Paper # | SDM2009-109,ICD2009-25 |
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Conference Information | |
Committee | SDM |
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Conference Date | 2009/7/9(1days) |
Place (in Japanese) | (See Japanese page) |
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Topics (in Japanese) | (See Japanese page) |
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Paper Information | |
Registration To | Silicon Device and Materials (SDM) |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | Study of stacked NAND type MRAM for universal memory |
Sub Title (in English) | |
Keyword(1) | Non-volatile |
Keyword(2) | MRAM |
Keyword(3) | spin transistor |
Keyword(4) | stacked NAND structure |
Keyword(5) | universal memory |
1st Author's Name | Shoto TAMAI |
1st Author's Affiliation | Graduate school of Electrical and Information Engineering, Shonan Institute of Technology() |
2nd Author's Name | Shigeyoshi WATANABE |
2nd Author's Affiliation | Graduate school of Electrical and Information Engineering, Shonan Institute of Technology |
Date | 2009-07-17 |
Paper # | SDM2009-109,ICD2009-25 |
Volume (vol) | vol.109 |
Number (no) | 133 |
Page | pp.pp.- |
#Pages | 6 |
Date of Issue |