Presentation 2009-09-25
High Throughput Irregular LDPC Decoder Based on High-Efficiency Column Operation Unit for IEEE802.11n Standard
Akiyuki NAGASHIMA, Nozomu TOGAWA, Masao YANAGISAWA, Tatsuo OHTSUKI,
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Abstract(in English) Low Density Parity Check (LDPC) code is expected to be an error correcting code for next generation networks since it shows high error correcting performance and is incorporated into IEEE802.11n, the next standard of wireless network. In this paper, we propose a multi-rate compatible irregular LDPC decoder enhancing column operation parallelism. Focusing on column-wise parallelism of column operations, our LDPC decoder increases usage rate of operational units and throughput by calculating all inputs simultaneously. The decoder achieves 28% increase in throughput compared to resent architectures.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) LDPC decoder / Irregular / Multi-Rate / column operation
Paper # VLD2009-38
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Committee VLD
Conference Date 2009/9/17(1days)
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Registration To VLSI Design Technologies (VLD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) High Throughput Irregular LDPC Decoder Based on High-Efficiency Column Operation Unit for IEEE802.11n Standard
Sub Title (in English)
Keyword(1) LDPC decoder
Keyword(2) Irregular
Keyword(3) Multi-Rate
Keyword(4) column operation
1st Author's Name Akiyuki NAGASHIMA
1st Author's Affiliation Dept. of Computer Science and Engineering, Waseda University()
2nd Author's Name Nozomu TOGAWA
2nd Author's Affiliation Dept. of Computer Science and Engineering, Waseda University
3rd Author's Name Masao YANAGISAWA
3rd Author's Affiliation Dept. of Computer Science and Engineering, Waseda University
4th Author's Name Tatsuo OHTSUKI
4th Author's Affiliation Dept. of Computer Science and Engineering, Waseda University
Date 2009-09-25
Paper # VLD2009-38
Volume (vol) vol.109
Number (no) 201
Page pp.pp.-
#Pages 6
Date of Issue