| Presentation | 2009-09-25 An Approach for Algorithm Tuning Power Grid Simulation by GPGPU Makoto YOKOTA, Yuuya ISODA, Hisako SUGANO, Ittetsu TANIGUCHI, Masahiro FUKUI, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | This paper proposes a speeding up technique for massively parallel power gird simulator by GPGPU (General Purpose computing on Graphics Processing Unit). The proposed power grid simulator is implemented by considering the GPU architecture. Experimental results show that the proposed power grid simulator has achieved 71 times speeding-up than CPU computation with same accuracy. It is observed that the proposed method speeds up the computation 2.9 times. |
| Keyword(in Japanese) | (See Japanese page) |
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| Paper # | VLD2009-36 |
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| Committee | VLD |
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| Conference Date | 2009/9/17(1days) |
| Place (in Japanese) | (See Japanese page) |
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| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | VLSI Design Technologies (VLD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | An Approach for Algorithm Tuning Power Grid Simulation by GPGPU |
| Sub Title (in English) | |
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| 1st Author's Name | Makoto YOKOTA |
| 1st Author's Affiliation | Science and Engineering, Ritsumeikan University() |
| 2nd Author's Name | Yuuya ISODA |
| 2nd Author's Affiliation | Science and Engineering, Ritsumeikan University |
| 3rd Author's Name | Hisako SUGANO |
| 3rd Author's Affiliation | Science and Engineering, Ritsumeikan University |
| 4th Author's Name | Ittetsu TANIGUCHI |
| 4th Author's Affiliation | Science and Engineering, Ritsumeikan University |
| 5th Author's Name | Masahiro FUKUI |
| 5th Author's Affiliation | Science and Engineering, Ritsumeikan University |
| Date | 2009-09-25 |
| Paper # | VLD2009-36 |
| Volume (vol) | vol.109 |
| Number (no) | 201 |
| Page | pp.pp.- |
| #Pages | 6 |
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